Design of Generic Floating Point Multiplier and Adder/Subtractor Units

被引：4
|
作者：
Hamid, Lamiaa S. A. [1 ]
Shehata, Khaled A. [2 ]
El-Ghitani, Hassan [1 ]
ElSaid, Mohamed [3 ]
机构：
[1] Misr Int Uni, ECE Dept, Cairo, Egypt
[2] Arab Acad Sci & Technol, ECE Dept, Cairo, Egypt
[3] Ain Shamis Univ, ECE Dept, Cairo, Egypt
来源：
2010 12TH INTERNATIONAL CONFERENCE ON COMPUTER MODELLING AND SIMULATION (UKSIM) | 2010年
关键词：
floating point; FPGA; Pipelined Architecture; HIGH-PERFORMANCE;
D O I：
10.1109/UKSIM.2010.117
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and used in the multiplier implementation. The new algorithm depends on dividing the multiplication operation into several smaller multiplications performed in parallel. The output from these multiplications is then manipulated in a manner to give the final result of the original multiplication operation. The adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm. In order to achieve high maximum, speed, both units were deeply pipelined. The design is written using VHDL code and mapped to Virtex2, Virtex4 and Virtex5 FPGAs. Both units can operate at more than 400 MHz on Virtex4.
引用
收藏
页码：615 / 618
页数：4
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