Novel FPGA-based low-cost hardware architecture for the PRESENT block cipher

被引：27

作者：

Lara-Nino, Carlos Andres ^{[1
]}

Morales-Sandoval, Miguel ^{[1
]}

Diaz-Perez, Arturo ^{[1
]}

机构：

[1] IPN, Unidad Tamaulipas, Ctr Invest & Estudios Avanzados, Ciudad Victoria, Tamaulipas, Mexico

来源：

19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016) | 2016年

关键词：

D O I：

10.1109/DSD.2016.46

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a novel FPGA-based design for the lightweight block cipher PRESENT and its implementation results. The proposed design allows to study area-performance trade-offs and thus constructing smaller or faster implementations. When optimized by area, the proposed design exhibits smaller latency and fewer FPGA resources than representative related works in the literature.

引用

页码：646 / 650

页数：5

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