Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space

被引:8
作者
Gomez-Pau, Alvaro [1 ]
Balado, Luz [1 ]
Figueras, Joan [1 ]
机构
[1] Univ Politecn Cataluna, BarcelonaTech, Dept Elect Engn, E-08028 Barcelona, Spain
关键词
Alternate test; analog and mixed-signal test; analog filter; Butterworth filter; classifiers; feature selection; octrees; production binning; quadtrees; quality binning; quality metrics; signature selection; specification binning; ANALOG; CIRCUITS; DESIGN;
D O I
10.1109/TCAD.2015.2501309
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customer's quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is 5x times faster using octrees than using the SVM-based classifier.
引用
收藏
页码:1386 / 1395
页数:10
相关论文
共 37 条
[21]   Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models [J].
Huang, Ke ;
Kupp, Nathan ;
Xanthopoulos, Constantinos ;
Makris, Yiorgos ;
Carulli, John M., Jr. .
IEEE DESIGN & TEST, 2015, 32 (01) :53-60
[22]   A new measure of rank correlation [J].
Kendall, MG .
BIOMETRIKA, 1938, 30 :81-93
[23]  
Kim S, 2007, INT SYM PERFORM ANAL, P1
[24]   Using Selective Voltage Binning to Maximize Yield [J].
Lichtensteiger, Susan ;
Bickford, Jeanne Paulette .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2013, 26 (04) :436-441
[25]  
Meagher D. J., 1980, Tech. Rep. IPLTR-80-111
[26]  
Mendes A., 2014, XXI Congresso Brasileiro de Custos-Natal, RN, Brasil, DOI 10.1109/ FIE.2014.7044086
[27]   A tutorial introduction to research on analog and mixed-signal circuit testing [J].
Milor, LS .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1998, 45 (10) :1389-1407
[28]  
Mohan P.V.A, 2012, VLSI ANALOG FILTERS
[29]   Signature analysis for analog and mixed-signal circuit test response compaction [J].
Nagi, N ;
Chatterjee, A ;
Yoon, HY ;
Abraham, JA .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (06) :540-546
[30]   Estimating error rate in defective logic using signature analysis [J].
Pan, Zhaoliang ;
Breuer, Melvin A. .
IEEE TRANSACTIONS ON COMPUTERS, 2007, 56 (05) :650-661