Beneath-the-channel strain-transfer-structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs

被引：13

作者：

Ang, Kah-Wee ^{[1
]}

Lin, Jianqiang ^{[1
]}

Tung, Chih-Hang ^{[2
]}

Balasubramanian, N. ^{[2
]}

Samudra, Ganesh ^{[1
]}

Yeo, Yee-Chia ^{[1
]}

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 117576, Singapore

[2] Inst Microelect, Singapore 117685, Singapore

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339719

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the first demonstration of a novel transistor structure featuring a beneath-the-channel strain-transfer-structure (STS) and embedded source/drain (S/D) stressors for strain and performance enhancement. As compared to a transistor with standard S/D stressors, additional strain is imparted to the channel region by the STS due to coupling of its lattice interactions with the adjacent S/D stressors and the overlying channel region. Both strained n-FET with SiGe STS and silicon-carbon (SiC) S/D, and strained p-FET with SiC STS and SiGe S/D, were realized. The I performance of strained n- and p-FETs with STS and S/D stressors were enhanced by 42% and 60%, respectively, over unstrained control transistors for given DIBL of 0.15 V/V.

引用

页码：42 / +

页数：2

共 6 条

[1] Ang KW, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P1069
[2] ANG KW, 2006, S VLSI TECH, P80
[3] [Anonymous], INT EL DEV M
[4] [Anonymous], 2003, IEEE INT ELECT DEVIC
[5] Horstmann M, 2005, INT EL DEVICES MEET, P243
[6] Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions
Yeo, Yee-Chia
[J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2007, 22 (01) : S177 - S182

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