Efficient Implementation of FPGA Based on Vivado High Level Synthesis

被引：0

作者：

Li, Huan ^{[1
]}

Ye, Wenhua ^{[1
,2
]}

机构：

[1] 36 Res Inst CETC, Jiaxing 314033, Zhejiang, Peoples R China

[2] Sci Technol Commun Informat Secur Control Lab, Jiaxing 314033, Zhejiang, Peoples R China

来源：

2016 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATIONS (ICCC) | 2016年

关键词：

FPGA; vivado; high level synthesis; C/C plus; language;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Xilinx Vivado High Level Synthesis (HLS) transforms a C specification into a register transfer level (RTL) implementation that can be synthesized into a Xilinx field programmable gate array (FPGA). It refers to the automatic integrated initially with C, C ++ or System C language to describe digital designs. Using HLS to explore all possibilities, analysis and performance characteristics of the area, and finalize a program to implement algorithms on FPGA chip. An example of a filter in this paper described the use of HLS to implement on FPGA quickly and efficiently.

引用

页码：2810 / 2813

页数：4