A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS

被引：30

作者：

Lin, Ying-Zu ^{[1
]}

Liu, Chun-Cheng ^{[1
]}

Huang, Guan-Ying ^{[1
]}

Shyu, Ya-Ting ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

来源：

2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

D O I：

10.1109/VLSIC.2010.5560246

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

引用

页码：243 / 244

页数：2