Efficient VLSI for Lempel-Ziv compression in wireless data communication networks

We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv (LZ)-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies [8], two semisystolli array architectures have been developed which are low power and area efficient, The first architecture trades off the compression speed for the area and has a low run-time overhead for multichannel compression. The second architecture achieves a high compression rate (one data symbol per clock) at the expense of the area due to a large clack load and global wiring, Compared to a recent state-of-the-art parallel architecture [14], our first array structure requires significantly less chip area (approximate to 330 k versus approximate to 36 k transistors) and more than an order of magnitude less power (approximate to 1.0 W versus approximate to 70 mW) while still providing the compression speed required for most data communication applications. Hence, data compression can be adopted in portable data communication as well as wireless local area networks. The second architecture has at least three times less area and power compared to [14] while providing the same constant compression rate. To demonstrate the correctness of our design, a prototype module for the first architecture has been implemented using 1.2 mu complementary metal-oxide-semiconductor (CMOS) technology. The compression module contains 32 simple and identical processors, has an average compression rate of 12.5 million bytes/s, and consumes 18.34 mW without the dictionary (approximate to 70 mW with a 4.1k SRAM for the dictionary) while operating at a 100 MHz clock rate (simulated).