Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric

被引：24

作者：

Jiang, Chunsheng ^{[1
]}

Liang, Renrong ^{[1
]}

Wang, Jing ^{[1
]}

Xu, Jun ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Tsinghua Natl Lab Informat Sci & Technol, Beijing 100084, Peoples R China

来源：

SOLID-STATE ELECTRONICS | 2016年 / 126卷

基金：

中国国家自然科学基金;

关键词：

Junctionless transistor; Ferroelectric gate dielectric; Negative capacitance; Power dissipation applications; Numerical simulation;

D O I：

10.1016/j.sse.2016.09.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferro-electric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart using numerical simulation. The steep subthreshold swing (SS < 60 mV/dec) is achieved at room temperature. The related physical mechanisms are discussed in detail. The low off-state current and high on/off current ratio could be obtained even for ultra-small transistors by optimizing the device parameters. NC-DG-JLTs have a great potential for low power dissipation applications. (C) 2016 Elsevier Ltd. All rights reserved.

引用

页码：130 / 135

页数：6

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