A low voltage current reuse LNA in a 130nm CMOS technology for UWB applications

A resistive current reuse UWB LNA implemented in a 130 nm CMOS technology is here reported. Covering a 2 to 9 GHz band, the circuit provides an 11.5 dB gain for a 4.45 dB minimum noise figure. Across the frequency band of interest, the NF is kept below 9 dB. The broadband behaviour of the input stage allows achieving a very wide input matching. As well Sit is lower than -12dB from 1 to 14.8GHz while bias current of reuse limits power consumption of the LNA core to 12 mA under 1.4V supply voltage. The chip size is here 0.63mm(2) including pads, thus depicting the lowest silicon area reported in the state of the art for such UWB LNA.