Numerical Evaluation of Thermal Resistance for Power MOSFET Packaged in Hermetic Method

被引:2
作者
Choi, Na-Yeon [1 ]
Zhang, Sung-Uk [1 ]
机构
[1] Dong Eui Univ, Digital Twin Lab, Busan, South Korea
基金
新加坡国家研究基金会;
关键词
Power MOSFET; Hermetic package; Thermal resistance; Finite element method;
D O I
10.1007/s42835-022-01013-6
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Power semiconductors are devices used to control high voltage. They are being used in various fields such as aviation, automobiles, and renewable energy generators. They require high reliability and high efficiency and have various evaluation criteria. Among them, thermal resistance characteristics are one of the important parameters that determine the heat dissipation capability of power semiconductors. In this study, the thermal resistance characteristics according to the change of the applied source-drain voltage through the electric-thermal multiple analysis by the power MOSFET were calculated through the finite element analysis. The equivalent electrical resistivity of the chip showed a significant change according to the change of the source-drain voltage. On the other hand, a small change was confirmed in the thermal resistance of the package. As a result, it can be seen that the change in applied V-GS affects the equivalent electrical resistivity of the chip but does not significantly affect the thermal resistance of the package stage.
引用
收藏
页码:1915 / 1920
页数:6
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