Strained Si/SiGe channel with buried Si0.99C0.01 for improved drivability, gate stack integrity and noise performance

被引：2

作者：

Loh, Wei-Yip ^{[1
]}

Zang, Hui

Oh, Hoon-Jung

Choi, Kyu-Jin

Nguyen, Hoai Son

Lo, Guo-Qiang

Cho, Byung Jin

机构：

[1] STAR, Inst Microelect, Singapore 117685, Singapore

[2] SEMATECH, Austin, TX 78741 USA

[3] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 119260, Singapore

[4] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 119260, Singapore

[5] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2007年 / 54卷 / 12期

关键词：

carbon; field-effect transistor; heterostructure; mobility; MOSFETs; SiGe; silicon;

D O I：

10.1109/TED.2007.908599

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a novel Si/Si1-xGex channel with improved noise, current drivability, and reliability using a buried Si0.99C0.01, which can induce higher channel strain for the same Ge concentration. High-kappa dielectrics on Si/Si1-xGex with buried Si0.99C0.01 show lower charge trapping, better leakage current distribution and less flatband voltage shift. Si/Si1-xGex channel p-MOSFET with the buried Si0.99C0.01 shows drive current improvement of up to 20% and better noise immunity.

引用

页码：3292 / 3298

页数：7

共 14 条

[1] Strained Si/SiGe MOS technology: Improving gate dielectric integrity
Olsen, S. H.
Yana, L.
Agaiby, R.
Escobedo-Cousin, E.
O'Neill, A. G.
Hellstrom, P. -E.
Ostling, M.
Lyutovich, K.
Kasper, E.
Claeys, C.
Parker, E. H. C.
MICROELECTRONIC ENGINEERING, 2009, 86 (03) : 218 - 223
[2] Performance of Trench Power MOSFET With Strained Si/SiGe Multilayer Channel
Sun, Shan
Yuan, Jiann-Shiun
Shen, Z. John
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (05) : 1517 - 1522
[3] 1/f noise study on strained Si0.8Ge0.2 p-channel MOSFETs with high-k/poly Si gate stack
Yan, L.
Simoen, E.
Olsen, S. H.
Akheyar, A.
Claeys, C.
O'Neill, A. G.
SOLID-STATE ELECTRONICS, 2009, 53 (11) : 1177 - 1182
[4] On the C-V characteristics of nanoscale strained gate-all-around Si/SiGe MOSFETs
Kumari, Amrita
Kumar, Subindu
Sharma, Tarun Kumar
Das, Mukul K.
SOLID-STATE ELECTRONICS, 2019, 154 : 36 - 42
[5] Strained-Si-strained-SiGe dual-channel layer structure as CMOS substrate for single workfunction metal-gate technology
Yu, SF
Jung, JW
Hoyt, JL
Antoniadis, DA
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (06) : 402 - 404
[6] Average drift mobility and apparent sheet-electron density profiles in strained-Si-SiGe buried-channel depletion-mode n-MOSFETs
Michelakis, K
Vilches, A
Papavassiliou, C
Despotopoulos, S
Fobelets, K
Toumazou, C
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (08) : 1309 - 1314
[7] Impact of virtual substrate quality on performance enhancements in strained Si/SiGe heterojunction n-channel MOSFETs
Olsen, SH
O'Neill, AG
Norris, DJ
Cullis, AG
Fobelets, K
Kemhadjian, HA
SOLID-STATE ELECTRONICS, 2003, 47 (08) : 1289 - 1295
[8] Low frequency noise in insulated-gate strained-Si n-channel modulation doped field effect transistors
Rumyantsev, Sergey L.
Fobelets, Kristel
Hackbarth, Thomas
Shur, Michael S.
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (7A): : 4011 - 4015
[9] High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack
Minamisawa, R. A.
Schmidt, M.
Oezben, E. Durgun
Lopes, J. M. J.
Hartmann, J. M.
Bourdelle, K. K.
Schubert, J.
Zhao, Q. T.
Buca, D.
Mantl, S.
MICROELECTRONIC ENGINEERING, 2011, 88 (09) : 2955 - 2958
[10] Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers
Duriez, B.
Vellianitis, G.
van Dal, M. J. H.
Doornbos, G.
Oxland, R.
Bhuwalka, K. K.
Holland, M.
Chang, Y. S.
Hsieh, C. H.
Yin, K. M.
See, Y. C.
Passlack, M.
Diaz, C. H.
2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,

← 1 2 →