A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

被引：54

作者：

Fukuda, Koji ^{[1
]}

Yamashita, Hiroki ^{[1
]}

Ono, Goichi ^{[1
]}

Nemoto, Ryo ^{[1
]}

Suzuki, Eiichi ^{[1
]}

Masuda, Noboru ^{[1
]}

Takemoto, Takashi ^{[1
]}

Yuki, Fumio ^{[1
]}

Saito, Tatsuya ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 12期

关键词：

Low power; serial link; transceiver; INTERFACE; RECOVERY; CIRCUIT;

D O I：

10.1109/JSSC.2010.2075410

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10(-12) or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

引用

页码：2838 / 2849

页数：12

共 17 条

[1] CLOCK RECOVERY FROM RANDOM BINARY SIGNALS [J].

ALEXANDER, JDH .

ELECTRONICS LETTERS, 1975, 11 (22) :541-542

[2] A scalable 5-15 Gbps, 14-75 mW low-power I/O (transceiver in 65 nm CMOS [J].

Balamurugan, Ganesh ;

Kennedy, Joseph ;

Banerjee, Gaurab ;

Jaussi, James E. ;

Mansuri, Mozhgan ;

O'Mahony, Frank ;

Casper, Bryan ;

Mooney, Randy .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) :1010-1019

[3] A 10-gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology [J].

Bulzacchelli, John F. ;

Meghelli, Mounir ;

Rylov, Sergey V. ;

Rhee, Woogeun ;

Rylyakov, Alexander V. ;

Ainspan, Herschel A. ;

Parker, Benjamin D. ;

Beakes, Michael P. ;

Chung, Aichin ;

Beukema, Troy J. ;

Pepejugoski, Petar K. ;

Shan, Lei ;

Kwark, Young H. ;

Gowda, Sudhir ;

Friedman, Daniel J. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2885-2900

[4]

Fukuda K., 2008, IEEE INT SOLID STATE, P98

[5] Power analysis for high-speed I/O transmitters [J].

Hatamkhani, H ;

Yang, CKK .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :142-145

[6]

Hu K, 2009, SYMP VLSI CIRCUITS, P46

[7] Low-power area-efficient high-speed I/O circuit techniques [J].

Lee, MJE ;

Dally, WJ ;

Chiang, P .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) :1591-1599

[8] A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling [J].

Leibowitz, Brian ;

Palmer, Robert ;

Poulton, John ;

Frans, Yohan ;

Li, Simon ;

Wilson, John ;

Bucher, Michael ;

Fuller, Andrew M. ;

Eyles, John ;

Aleksic, Marko ;

Greer, Trey ;

Nguyen, Nhat M. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (04) :889-898

[9] Aquabis(dichloroacetato-κO)(1,10-phenanthroline-κ2N,N′)copper(II) [J].

Liu, Yaru ;

Ning, Jianzhong ;

Sun, Junshan ;

Zhang, Chuan .

ACTA CRYSTALLOGRAPHICA SECTION E-STRUCTURE REPORTS ONLINE, 2009, 65 :M113-U1146

[10] A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking [J].

Miki, Y ;

Saito, T ;

Yamashita, H ;

Yuki, F ;

Baba, T ;

Koyama, A ;

Sonehara, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (04) :613-621

← 1 2 →