Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on low-frequency noise (LFN) was carried out for the commercial 1.2-kV/30-A silicon carbide (SiC) power MOSFETs under repetitive short-circuit (SC) stress. The experiment results show that the on-state resistance (R-dson) and threshold voltage (V-th) increase significantly. Meanwhile, the drain-source current (I-ds) decreases obviously with the increase of the SC cycles. Furthermore, the gate-source leakage current (I-gss) of the SiC power MOSFETs increase greatly and the blocking characteristics deteriorated after 1000 SC cycles. The positive shift was observed on the gate-capacitance versus gate-voltage (C-g-V-g) curve, which shows that the damage region could be in channel along the SiC/SiO2 interface after repetitive SC stress. In order to obtain the trap information, trap characterization was performed by using LFN method, and the LFN results show that the trap density increases with the SC cycles. The physical mechanism could be attributed to electrically active traps generated at SiC/SiO2 interface and oxide layer due to the peak ionization rate, the perpendicular electrical field and high temperature during SC stress. The study may be useful to provide reference for converters design and fault protection of SiC power MOSFETs.