Further minimization of BDDS of large circuits with XOR/XNOR recognition

In this paper we propose an XOR/XNOR pattern based dynamic reordering method. The algorithm follows the main routine of sifting [8), additionally explores some inner structures, i.e., the XOR/XNOR patterns, of BDDs. Experimental results show that our method can reduce BDDs' size further, especially those of large circuits, while CPU times are comparable with other dynamic reordering techniques.