A 0.5-V 0.42.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip

被引：88

作者：

Cheng, Kuo-Hsing ^{[1
]}

Tsai, Yu-Chang ^{[1
]}

Lo, Yu-Lung ^{[2
]}

Huang, Jing-Shiuan ^{[3
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, MSIC Lab, Jhongli 32001, Taoyuan County, Taiwan

[2] Natl Kaohsiung Normal Univ, Dept Elect Engn, Kaohsiung 824, Taiwan

[3] Realtek Semicond Corp, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2011年 / 58卷 / 05期

关键词：

Charge pump (CP); low-voltage segmented current mirror (LV-SCM); multi-phase VCO; phase-locked loop (PLL); system-on-chips (SoCs); LOW-VOLTAGE; CMOS; PLL; POWER;

D O I：

10.1109/TCSI.2010.2089559

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain (K-VCO), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular V-T (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is -87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW(excluding the buffers). The core area is 0.074 mm(2).

引用

页码：849 / 859

页数：11

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