共 28 条
[1]
[Anonymous], P 2017 IEEE 35 VLSI, DOI DOI 10.1109/VTS.2017.7928930
[2]
[Anonymous], IEEE T EMERG TOPICS
[3]
[Anonymous], IEEE T EMERG TOPICS
[8]
A Hybrid DMR latch to tolerate MNU using TDICE and WDICE
[J].
2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS),
2018,
:121-126