Rule-Based Design for Multiple Nodes Upset Tolerant Latch Architecture

被引:19
作者
Sajjade, Faisal Mustafa [1 ,2 ]
Goyal, Neeraj Kumar [1 ]
Varaprasad, B. K. S. V. L. [3 ]
机构
[1] Indian Inst Technol Kharagpur, Subir Chowdhury Sch Qual & Reliabil, Kharagpur 721302, W Bengal, India
[2] UR Rao Satellite Ctr, Reliabil & Qual Assurance Elect & Opt Syst Grp, Bengaluru 560017, India
[3] UR Rao Satellite Ctr, Adv Chip Design Div, Bengaluru 560017, India
关键词
Multiple nodes upset mechanisms; RHBD latch; rule-based design; double node upset tolerant latch; multi-pronged fork buffer; SINGLE-EVENT TRANSIENTS; CELLS;
D O I
10.1109/TDMR.2019.2945917
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Many radiation hardened by design (RHBD) latch architectures have been presented in the literature. These architectures are designed such that these can tolerate a charged particle impact at multiple nodes of the latch. These architectures differ in terms of approach for developing single event upset (SEU) tolerance, area and other parameters. The literature survey and SEU fault simulation study reveal that some of the architectures have SEU critical internal node pairs while most of the architectures exhibit single point failure at input data node. In this work, SEU mechanisms in RHBD latches are analyzed and a new rule-based design is proposed for designing latches which can tolerate multiple nodes upset. Critical charge (Q(crit)) of the proposed latch architecture is found significantly higher than most of double node upset tolerant latches published. Area requirement, power consumption, and performance of the proposed latch are found comparable with the latches of same class. The proposed rule-based design methodology may become helpful in developing a computer-aided design tool for synthesis of multiple nodes upset tolerant latch.
引用
收藏
页码:680 / 687
页数:8
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