Effects of Fin shape on sub-10 nm FinFETs

被引:16
作者
Yu, Zhihao [1 ]
Chang, Sheng [1 ]
Wang, Hao [1 ]
He, Jin [1 ]
Huang, Qijun [1 ]
机构
[1] Wuhan Univ, Sch Phys & Technol, Dept Elect Sci & Technol, Wuhan 430072, Hubei, Peoples R China
基金
中国国家自然科学基金;
关键词
FinFET; Fin shape; NEGF; Fin ratio factor; NanoTCAD; LINE-EDGE ROUGHNESS; DEVICE; IMPACT;
D O I
10.1007/s10825-015-0677-1
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As a successful novel structure, FinFET has been a hot research area, whereas how Fin influences FinFETs' performance on the hypothetical silicon process limitation is still an open issue. In reported works, Fin shape was normally mixed with the change of other parameters, such as the size scaling, and its effect was confused by those. In this paper, we just focus on Fin shape's effect itself. A simple and quantitative two-incline-angle description of Fin shape is proposed. Using this method, four typical (trapezoidal, rectangular, convex and concave) Fins' control abilities upon the hypothetical silicon limitation process node (sub-10 nm) are analyzed, and their impacts on FinFETs' characteristics are discussed systematically. The results show that in this case the rectangle shape Fin is prior on both analog and digital characteristics. The Fin shape's influence on FETs' frequency characteristic is not obvious. As an in-depth exploration, a ratio factor between the effective channel width and the cross-section area of channel is pointed out. The proposed factor can quantitatively evaluate Fin's impact not only for the regular shape Fins but also for the irregular ones. This work gives a guidance of FinFET's design on both nano scale silicon FinFETs and other advanced material FinFETs.
引用
收藏
页码:515 / 523
页数:9
相关论文
共 24 条
  • [1] Analog circuits in ultra-deep-submicron CMOS
    Annema, AJ
    Nauta, B
    van Langevelde, R
    Tuinhout, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (01) : 132 - 143
  • [2] [Anonymous], DIAGN MULT SLOW GAT
  • [3] [Anonymous], 2013 IEEE INT EL DEV
  • [4] Impact of line-edge roughness on FinFET matching performance
    Baravelli, Ernanuele
    Dixit, Abhisek
    Rooyackers, Rita
    Jurczak, Malgorzata
    Speciale, Nicolo
    De Meyer, Kristin
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (09) : 2466 - 2474
  • [5] Bühler RT, 2010, IEEE INT SOI CONF
  • [6] Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape
    Buehler, R. T.
    Giacomini, R.
    Pavanello, M. A.
    Martino, J. A.
    [J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2009, 24 (11)
  • [7] Chang Yong Kang, 2013, 2013 Symposium on VLSI Technology, pT90
  • [8] Choi JA, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P647
  • [9] Colinge JP, 2008, INTEGR CIRCUIT SYST, P1, DOI 10.1007/978-0-387-71752-4_1
  • [10] Three-dimensional simulation of one-dimensional transport in silicon nanowire transistors
    Fiori, Gianluca
    Iannaccone, Giuseppe
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2007, 6 (05) : 524 - 529