A study on VLSI implementation of image enhancement techniques

被引:0
作者
Aklak, Annis Fathima [1 ]
Pugazhenthi, Murugesh Yadhav [2 ]
Alex, John Sahaya Rani [3 ]
机构
[1] Vellore Inst Technol, Sch Elect Engn, Chennai, Tamil Nadu, India
[2] BlueBird Electromech Contracting LLC, Ajman, U Arab Emirates
[3] Vellore Inst Technol, Ctr Healthcare Adv Innovat & Res, Chennai, Tamil Nadu, India
关键词
field programmable gate array; floating point multiplier; image enhancement; HARDWARE IMPLEMENTATION; FPGA IMPLEMENTATION; FLOATING-POINT; MULTIPLIER; ARCHITECTURE; ALGORITHMS; HISTOGRAM; DESIGN; COMPUTATION; FEATURES;
D O I
10.1002/cpe.6734
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
In real-time, the images captured are not always appreciable for visual perception. The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real-time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large-scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma-transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA.
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页数:11
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