Portable digital clock generator for digital signal processing applications

被引：4

作者：

Olsson, T ^{[1
]}

Nilsson, P ^{[1
]}

机构：

[1] Lund Univ, Dept Electrosci, SE-22100 Lund, Sweden

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 19期

关键词：

D O I：

10.1049/el:20030910

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully integrated clock generator with behaviour similar to a PLL is proposed. A free-running ring oscillator is used as internal clock and the output clock is generated using two counters. The clock generator is described in synthesisable VHDL-code and can therefore easily be made from standard cells found in any commercial standard CMOS cell library.

引用

页码：1372 / 1374

页数：3