Modeling layout effects for sensitivity-based analog circuit optimization

Successful deep-submicron designs require significant computation resources for thorough signal and design integrity analysis. Rising quality expectations and shortening time-to-market requirements present additional challenges for design closure. Conventional analog circuit optimizers are efficient in circuit analysis and optimization. Due to recent promising results, designers begin to adopt automated physical synthesis in their condensed development cycles in order to improve their prototyping efficiency. For high-performance circuits optimization, idealized performance as well as parasitic data should also be considered. This paper presents an effective framework to incorporate parasitic effects into a sensitivity-based circuit optimization tool. To relieve the physical synthesis bottleneck, estimations of parasitic values based on past extraction results are made during incremental design changes. Sensitivities of the performance impact can then be computed efficiently. As a result physical performance can be optimized using available optimizer and synthesis tools without the need of a priori expert rules, knowledge or cell libraries.