FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations

被引：0
|
作者：
Siripurapu, Srinivas [1 ]
Gayasen, Aman [2 ]
Gopalakrishnan, Padmini [2 ]
Chandrachoodan, Nitin [1 ]
机构：
[1] Indian Inst Technol Madras, Chennai, Tamil Nadu, India
[2] Xilinx Inc, San Jose, CA USA
来源：
FPGA'17: PROCEEDINGS OF THE 2017 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS | 2017年
关键词：
High performance computation; NUDFT; Wireless channel simulation; FPGAs; acceleration; high-level synthesis;
D O I：
10.1145/3020078.3021800
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：295 / 295
页数：1
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