Verification Approach Based on Emulation Technology

被引：0

作者：

Koczor, Arkadiusz ^{[1
]}

Matoga, Lukasz ^{[1
]}

Penkala, Piotr ^{[1
]}

Pawlak, Adam ^{[2
]}

机构：

[1] Evatronix SA, Bielsko Biala, Poland

[2] Silesian Tech Univ, Inst Elect, Gliwice, Poland

来源：

2016 IEEE 19TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS) | 2016年

关键词：

design verification; emulation platform; debugging; FPGA-in-the-Loop; co-simulation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents a scalable architecture for fast emulation of Systems-on-Chip. It is implemented on a dedicated modular FPGA-based hardware platform. This verification ecosystem presents a new approach to improve efficiency of the verification process through hardware-based acceleration of tests. The system consists of dedicated hardware modules and third-party; easy-to-get evaluation boards to provide an affordable solution for SMEs with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, and connectors, the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. It provides a debug capability which enables quick identification and elimination of implementation bugs. The paper also reports on the use of the emulation environment in FPGA-in-the-Loop simulation. This solution may be applied to a broad range of applications.

引用

页码：169 / 174

页数：6

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