Comprehensive Variability Analysis in Dual-Port FeFET for Reliable Multi-Level-Cell Storage

-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage () states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness () from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in are reduced for BG read on reducing, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled . We demonstrate that dual-port FeFET with BG read and scaled offers MLC storage of 3 bits.