A novel type of CMOS image sensor (CIS) leveraging two types of analog-to-digital converters (ADCs) is presented in this work. Contrary to conventional EA image sensors, which implement Sigma Delta ADCs at the column or pixel array level, this work utilizes the pixel structure as part of the Sigma Delta modulator to enhance the noise shaping capabilities of the readout scheme. The overall speed performance of this indirect feedback (IF) Sigma Delta image sensor is enhanced with the addition of a Successive Approximation Register (SAR) startup. The SAR startup has been successfully demonstrated on two prototype image sensors developed in a generic 0.35 mu m digital CMOS process. For the column-level, 320x180 pixel implementation, the SAR startup is included with minimal additional overhead, 1.8% of original Sigma Delta column readout circuitry.
