Packet scheduling in proteo network-on-chip

This paper presents three different packet scheduling algorithms specially suited for intra-chip packet-switching networks, called Networks-on-Chip (NoC), because of their simplicity. Their relative performance is evaluated in terms of total bandwidth, delay, delay jitter and fairness in the distribution of network resources. The system used for simulation is a particular instance of our NoC proposal, called Proteo, which is briefly introduced. The simulation environment is based on VHDL and Python. A brief study on the effects of local variation of scheduling parameters is included. It is shown that it is possible to control bandwidth and delay in this way.