Packet scheduling in proteo network-on-chip

被引：0

作者：

Tortos, DAS ^{[1
]}

Nurmi, J ^{[1
]}

机构：

[1] Tampere Univ Technol, Inst Digital & Comp Sci, FIN-33101 Tampere, Finland

来源：

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks | 2004年

关键词：

network-on-chip; packet scheduling; network simulation;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents three different packet scheduling algorithms specially suited for intra-chip packet-switching networks, called Networks-on-Chip (NoC), because of their simplicity. Their relative performance is evaluated in terms of total bandwidth, delay, delay jitter and fairness in the distribution of network resources. The system used for simulation is a particular instance of our NoC proposal, called Proteo, which is briefly introduced. The simulation environment is based on VHDL and Python. A brief study on the effects of local variation of scheduling parameters is included. It is shown that it is possible to control bandwidth and delay in this way.

引用

页码：116 / 121

页数：6

共 50 条

[21] On network-on-chip comparison
Salminen, Erno
Kulmala, Ari
Hamalainen, Timo D.
DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 503 - 510
[22] The Runahead Network-On-Chip
Li, Zimo
Miguel, Joshua San
Jerger, Natalie Enright
PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA-22), 2016, : 333 - 344
[23] Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture
Munirul, Haque Mohammad
Hasegawa, Tomoaki
Kameyama, Michitaka
ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, 2006, : 38 - 43
[24] Flexible parallel pipeline Network-on-Chip based on dynamic packet identity management
Samman, Faizal A.
Hollstein, Thomas
Glesner, Manfred
2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8, 2008, : 3305 - 3312
[25] A survey on mapping and scheduling techniques for 3D Network-on-chip
Kaur, Simran Preet
Ghose, Manojit
Pathak, Ananya
Patole, Rutuja
JOURNAL OF SYSTEMS ARCHITECTURE, 2024, 147
[26] Network-on-Chip Aware Scheduling of Hard-Real-Time Tasks
Shekhar, Mayank
Ramaprasad, Harini
Mueller, Frank
2014 9TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES), 2014,
[27] Integrated mapping and scheduling for circuit-switched network-on-chip architectures
Chi, Hsin-Chou
Wu, Chia-Ming
Lee, Jun-Hui
DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 415 - 420
[28] Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems
Yusuf, Bichi Bashir
Maqsood, Tahir
Rehman, Faisal
Madani, Sajjad A.
IEEE ACCESS, 2021, 9 : 38778 - 38791
[29] MPCC: Multi-path Routing Packet Connect Circuit for Network-on-Chip
Du, Gaoming
Yang, Xin
Chen, Fuzhan
Zhang, Duoli
Song, Yukun
Peng, Chen
2015 IEEE 9TH INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION (ASID), 2015, : 86 - 91
[30] RPNoC: A Ring-Based Packet-Switched Optical Network-on-Chip
Wang, Xiaolu
Gu, Huaxi
Yang, Yintang
Wang, Kun
Hao, Qinfen
IEEE PHOTONICS TECHNOLOGY LETTERS, 2015, 27 (04) : 423 - 426

← 1 2 3 4 5 →