Effect of Cu damascene metallization on gate SiO2 plasma damage

被引:0
|
作者
Bang, DS [1 ]
Hao, MY [1 ]
Chen, S [1 ]
Xiang, Q [1 ]
Yeap, G [1 ]
Lin, MR [1 ]
机构
[1] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
来源
1998 3RD INTERNATIONAL SYMPOSIUM ON PLASMA PROCESS-INDUCED DAMAGE | 1998年
关键词
D O I
10.1109/PPID.1998.725575
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The effect of using a Cu damascene process on plasma process-induced damage (PPID) is studied in relationship to future scaling rules. Wafers processed using: a Cu damascene metallization scheme show little increase in gate leakage as antenna ratios are increased. This is contrasted to conventional Al wafers, which show a significant increase in the gate leakage as the antenna ratio is increased. Applying this result to future technology generations shows that wafers produced with a Cu damascene process have the potential to exhibit significantly less gale leakage for future technology generations.
引用
收藏
页码:64 / 67
页数:4
相关论文
共 50 条
  • [1] A Study on Seed Damage in Plating Electrolyte and Its Repairing in Cu Damascene Metallization
    Cho, Sung Ki
    Lim, Taeho
    Lee, Hong-Kee
    Kim, Jae Jeong
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2010, 157 (04) : D187 - D192
  • [2] Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture
    Motte, P
    Torres, J
    Palleau, J
    Tardif, F
    Demolliens, O
    Bernard, H
    MICROELECTRONIC ENGINEERING, 2000, 50 (1-4) : 487 - 493
  • [3] Comparison of plasma-induced damage in SiO2/TiN and HfO2/TiN gate stacks
    Young, C. D.
    Bersuker, G.
    Zhu, F.
    Matthews, K.
    Choi, R.
    Song, S. C.
    Park, H. K.
    Lee, J. C.
    Lee, B. H.
    2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 67 - +
  • [4] GATE SIO2 BREAKDOWN ANALYSIS IN PLASMA-ETCHING
    MITSUHASHI, T
    KANAMARI, J
    SOGOH, K
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1986, 133 (06) : C226 - C226
  • [5] Effect of annealing on preferred orientations in the Cu/SiO2 and Cu/SiO2/Si(100) interfaces
    Bagalagel, S.
    Shirokoff, J.
    MATERIALS SCIENCE AND ENGINEERING A-STRUCTURAL MATERIALS PROPERTIES MICROSTRUCTURE AND PROCESSING, 2008, 479 (1-2): : 112 - 116
  • [6] Multilevel test structures for metal CMP integration - Application to Cu/SiO2 damascene interconnect
    Fayolle, M
    Gayet, P
    Morand, Y
    PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, : 28 - 30
  • [7] Periodic reverse electrodeposition of (111)-oriented nanotwinned Cu in small damascene SiO2 vias
    Yang, Shih-Chi
    Tran, Dinh-Phuc
    Ong, Jia-Juen
    Chiu, Wei -Lan
    Chang, Hsiang -Hung
    Chen, Chih
    JOURNAL OF ELECTROANALYTICAL CHEMISTRY, 2023, 935
  • [8] Effect of SiO2/Si interface roughness on gate current
    Mao, LF
    Yang, Y
    Wei, JL
    Zhang, HQ
    Xu, MZ
    Tan, CH
    MICROELECTRONICS RELIABILITY, 2001, 41 (11) : 1903 - 1907
  • [9] Characterization and Adhesion in Cu/Ru/SiO2/Si Multilayer Nano-scale Structure for Cu Metallization
    N. Chawla
    S. H. Venkatesh
    D. R. P. Singh
    T. L. Alford
    Journal of Materials Engineering and Performance, 2013, 22 : 1085 - 1090
  • [10] Characterization and Adhesion in Cu/Ru/SiO2/Si Multilayer Nano-scale Structure for Cu Metallization
    Chawla, N.
    Venkatesh, S. H.
    Singh, D. R. P.
    Alford, T. L.
    JOURNAL OF MATERIALS ENGINEERING AND PERFORMANCE, 2013, 22 (04) : 1085 - 1090