共 15 条
[1]
Predicting inter-thread cache contention on a chip multi-processor architecture
[J].
11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS,
2005,
:340-351
[2]
Dybdahl H, 2007, INT S HIGH PERF COMP, P2
[3]
Hamerly G., 2005, J INSTRUCTION LEVEL, V7
[4]
Adaptive Insertion Policies for Managing Shared Caches
[J].
PACT'08: PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES,
2008,
:208-219
[5]
Jichuan Chang, 2007, 21st International Conference on Supercomputing. ICS 07, P242
[6]
Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling
[J].
32nd International Symposium on Computer Architecture, Proceedings,
2005,
:408-419
[7]
Lin J, 2008, INT S HIGH PERF COMP, P339
[8]
Loh G.H., 2009, INT S PERF AN SYST S
[9]
Qureshi MK, 2006, INT SYMP MICROARCH, P423
[10]
Qureshi MK, 2006, CONF PROC INT SYMP C, P167, DOI 10.1145/1150019.1136501