Cryogenic flip-chip for petaflop computing

Building computers with petaflop (10(15) operations per second) capability will require packaging technology capable of handling 10's of Gbit/second per data line, with literally millions of lines. Speed, power, and packing density requirements strongly suggest that the computational core of such a machine will rely on superconducting elements and wiring. We present the rep-level system design and preliminary experiments for cytogenic, high density packaging for such a next generation machine. Starting from the basic architectural requirements for a multi-threaded, multi-processor design, we are developing the key packaging technologies including flip-chip chip bonding and GHz cabling. To minimize interconnect inductance, we have demonstrated an indium-tin solder reflow process producing flip chip bonds less than 2 microns high. For silicon-to-silicon bonding, the process is quite robust. We have formed 6,400 connections on a 5-mm single chip without failure. The bumps support data transfer at 10 Gbit/second in a cryogenic environment with clean "eye" diagrams. The process is amenable to rework for chip replacement. We are also investigating specialized high-speed cabling for the cryogenic environment. The cables must simultaneously display low dispersion and low attenuation for 10 Gbit/second digital signals, while minimizing thermal conduction from warm to cold ends. We have optimized layer thicknesses and construction of polyimide/copper microstrip cables. We will present electrical, thermal, and mechanical measurements.