The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

被引：13

作者：

Olasupo, KR

Yarbrough, W

Hatalis, MK

机构：

[1] AT&T BELL LABS,ALLENTOWN,PA 18103

[2] LEHIGH UNIV,DEPT ELECT ENGN & COMP SCI,BETHLEHEM,PA 18105

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1996年 / 43卷 / 08期

关键词：

D O I：

10.1109/16.506785

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have examined the effect of drain offset structures with lengths ranging from 0.0 mu m to 1.0 mu m on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of channel lengths studied (1.0 mu m to 0.35 mu m) the optimum drain offset length was 0.35 mu m.

引用

页码：1306 / 1308

页数：3