Robust Clock Tree using Single-Well Cells for Multi-VT 28nm UTBB FD-SOI Digital Circuits

被引：0

作者：

Giraud, B. ^{[1
]}

Noel, J. P. ^{[2
]}

Abouzeid, F. ^{[2
]}

Clerc, S. ^{[2
]}

Thonnart, Y. ^{[1
]}

机构：

[1] CEA LETI MINATEC, Grenoble, France

[2] STMicroelectronics, Crolles, France

来源：

2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The 28nm UTBB FD-SOI design platform enables multi-V-T standard cells co-integration with independent back biases (BB). In this paper, we propose a new clock-tree cell to build a robust clock tree isolated from the various BB of the different V-T regions, showing better propagation and transition times balancing (2.5x), and a drastic skew reduction (5x at 0.4V) compared to a conventional clock tree.

引用

页数：2

共 14 条

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