Uniform current/voltage-sharing for interconnected DC-DC converters

This paper presents advanced interconnection and control approaches for three current-mode, shared-bus converter architectures: (1) parallel-input parallel-output (PIPO), (2) parallel-input series-output (PISO), and (3) series-input parallel-output (SIPO). Without proper control, non-uniform current sharing or voltage distribution may exist among interconnected DC-DC converters, negatively impacting reliability. Using the control schemes presented herein, reliable and robust power system performance is achievable from the series and/or parallel interconnection of commercial-off-the-shelf (COTS) DC-DC converters. In particular, PIPO connected COTS converters have been well-known and already achieved uniform current-sharing by using the provided parallel control port as a common "shared bus" for commanding the parallel-connected converters to operate as voltage-controlled current sources. This paper presents two control alternatives for PIPO converter systems based on the "shared-bus" approach: (1) minimum-voltage-error shared-bus and (2) maximum-voltage-error shared-bus. Furthermore, the current-mode shared-bus converters extend their applications to power system architectures configured as PISO and SIPO. Employing a PISO (or SIPO) interconnect method, current-mode COTS converters can transform their system input voltages to higher (or lower) system output voltages, provide flexibility for power system expansion, and preserve system efficiencies equal to that obtained from stand-alone converters. The system achieves robust stability and uniform voltage sharing among series-connected converters through unique output and input voltage distribution control approaches for the PISO and SIPO power architectures. Two effective approaches to uniform voltage distribution control, the central-limit (CL) and maximum-limit (ML) distribution, will be discussed. Both computer simulation and experimental prototypes validate both series-connected power converter architectures with the two control approaches. (1 2).