A two-bit-per-cell content-addressable memory using single-electron transistors

被引：4

作者：

Degawa, K ^{[1
]}

Aoki, T ^{[1
]}

Higuchi, T ^{[1
]}

Inokawa, H ^{[1
]}

Takahashi, Y ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan

来源：

35TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISMVL.2005.6

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents a circuit design of a two-bit-per-cell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 113 compared with the conventional CAM architecture.

引用

页码：32 / 38

页数：7

共 12 条

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