8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator

被引：17

作者：

Terada, J ^{[1
]}

Matsuya, Y ^{[1
]}

Morisawa, F ^{[1
]}

Kado, Y ^{[1
]}

机构：

[1] NTT, Telecommun Energy Labs, Kanagawa 2430198, Japan

来源：

PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS | 2000年

关键词：

D O I：

10.1109/APASIC.2000.896906

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at I V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.

引用

页码：53 / 56

页数：4