Design of Time-to-Digital converter output interface

被引：0
|
作者：
Miskowicz, Marek [1 ]
机构：
[1] AGH Univ Sci & Technol, Dept Elect, PL-30059 Krakow, Poland
来源：
2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A design of Time-to-Digital converter output interface for ADCs with asynchronous Sigma-Delta modulation is presented in details in the paper. The concept of the digital interface with double data buffering and asynchronous serial link is carefully explained on the basis of the schematics of particular functional blocks. The TDC design has been optimized in terms of minimizing the power consumption.
引用
收藏
页码：150 / 153
页数：4
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