Copper plating for 3D interconnects

被引：70

作者：

Radisic, A. ^{[1
]}

Luhn, O. ^{[1
]}

Philipsen, H. G. G. ^{[1
]}

El-Mekki, Z. ^{[1
]}

Honore, M. ^{[1
]}

Rodet, S. ^{[1
]}

Armini, S. ^{[1
]}

Drijbooms, C. ^{[1
]}

Bender, H. ^{[1
]}

Ruythooren, W. ^{[1
]}

机构：

[1] IMEC VZW, B-3001 Louvain, Belgium

来源：

MICROELECTRONIC ENGINEERING | 2011年 / 88卷 / 05期

关键词：

Copper; Cu; Plating; TSV; HIGH-ASPECT-RATIO; ELECTRODEPOSITION; VIAS; ADDITIVES; TRENCHES; CHEMISTRY; HOLES;

D O I：

10.1016/j.mee.2010.06.030

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we report on Cu plating of through-silicon-vias (TSV-s) using in-house made acidic Cu bath with model additives (SPS, PEG, and JGB). Although the model additives might not be as potent as commercial additives, they have been studied in detail, and their role in Cu plating has been described extensively in scientific literature. This in turn allows deeper insight into how changes in bath composition affect the plating mechanism and Cu via-fill. (C) 2010 Elsevier B.V. All rights reserved.

引用

页码：701 / 704

页数：4

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