Parallel Order ATPG for Test Compaction

被引：0

作者：

Chen, Yu-Wei ^{[1
]}

Ho, Yu-Hao ^{[1
]}

Chang, Chih-Ming ^{[1
]}

Yang, Kai-Chieh ^{[1
]}

Li, Ming-Ting ^{[1
]}

Li, James Chien-Mo ^{[1
]}

机构：

[1] Natl Taiwan Univ, Lab Dependable Syst LaDS, Grad Inst Elect Engn, Taipei, Taiwan

来源：

2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2018年

关键词：

parallel ATPG; test compaction; TEST SETS; CIRCUITS; GENERATION; PATTERNS; QUALITY;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we proposed a novel test compaction algorithm, called Parallel Order Dynamic Test Compaction (P0DTC). We show that the order of secondary faults within a single test generation is important for test compaction. We launch parallel ATPG with different orders of secondary faults and choose the best test pattern with the largest number of detected faults. Experimental results show that our test length is 48% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our test length for N-detect test sets is at least 1/4 shorter than that of the commercial ATPG.

引用

页数：4

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