Parallel Order ATPG for Test Compaction

被引：0

作者：

Chen, Yu-Wei ^{[1
]}

Ho, Yu-Hao ^{[1
]}

Chang, Chih-Ming ^{[1
]}

Yang, Kai-Chieh ^{[1
]}

Li, Ming-Ting ^{[1
]}

Li, James Chien-Mo ^{[1
]}

机构：

[1] Natl Taiwan Univ, Lab Dependable Syst LaDS, Grad Inst Elect Engn, Taipei, Taiwan

来源：

2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2018年

关键词：

parallel ATPG; test compaction; TEST SETS; CIRCUITS; GENERATION; PATTERNS; QUALITY;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we proposed a novel test compaction algorithm, called Parallel Order Dynamic Test Compaction (P0DTC). We show that the order of secondary faults within a single test generation is important for test compaction. We launch parallel ATPG with different orders of secondary faults and choose the best test pattern with the largest number of detected faults. Experimental results show that our test length is 48% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our test length for N-detect test sets is at least 1/4 shorter than that of the commercial ATPG.

引用

页数：4

共 50 条

[31] Compaction of IDDQ Test Sequence Using Reassignment Method
Toshiyuki Maeda
Kozo Kinoshita
Journal of Electronic Testing, 2000, 16 : 243 - 249
[32] Compaction of IDDQ test sequence using reassignment method
Maeda, T
Kinoshita, K
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2000, 16 (03): : 243 - 249
[33] Efficient test compaction for pseudo-random testing
Zhang, S
Seth, SC
Bhattacharya, BB
14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 337 - 342
[34] Target Faults for Test Compaction Based on Multicycle Tests
Pomeranz, Irith
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 25 (02)
[35] A Compaction Method for STLs for GPU in-field test
Guerrero-Balaguera, Juan-David
Condia, Josie E. Rodriguez
Reorda, Matteo Sonza
PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, : 454 - 459
[36] A Don't Care Identification Method for Test Compaction
Yamazaki, Hiroshi
Wakazono, Motohiro
Hosokawa, Toshinori
Yoshimura, Masayoshi
PROCEEDINGS OF THE 2013 IEEE 16TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2013, : 215 - 218
[37] Test Compaction by Backward and Forward Extension of Multicycle Tests
Pomeranz, Irith
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (01) : 242 - 246
[38] Test Compaction Under Bounded Transparent-Scan
Pomeranz, Irith
2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS), 2019,
[39] Switching Activity as a Test Compaction Heuristic for Transition Faults
Pomeranz, Irith
Reddy, Sudhakar M.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (09) : 1357 - 1361
[40] Path delay test compaction with process variation tolerance
Kajihara, S
Fukunaga, M
Wen, XQ
Maeda, T
Hamada, S
Sato, Y
42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005, 2005, : 845 - 850

← 1 2 3 4 5 →