Fault Tolerance in FPGA Architecture Using Hardware Controller-Design Approach

With advancement in process technology, the feature size is decreasing which leads to higher defect densities. More sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield. The design is implemented using FPGA Altera Quartus II EC121Q240C6.