Logic Computing with Stateful Neural Networks of Resistive Switches

被引:130
作者
Sun, Zhong [1 ,2 ]
Ambrosi, Elia [1 ,2 ]
Bricalli, Alessandro [1 ,2 ]
Ielmini, Daniele [1 ,2 ]
机构
[1] Politecn Milan, Dipartimento Elettron Informaz & Bioingn, Piazza L da Vinci 32, I-20133 Milan, Italy
[2] IU NET, Piazza L da Vinci 32, I-20133 Milan, Italy
基金
欧洲研究理事会;
关键词
in-memory computing; neural networks; neuromorphic; resistive switching memory; stateful logic; PART I; THRESHOLD; OPERATIONS; DRIVEN; DEVICE;
D O I
10.1002/adma.201802554
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
Brain-inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal-oxide-semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two-input logic operations with just one step, except for the exclusive-OR (XOR) needing two sequential steps. 1-bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.
引用
收藏
页数:8
相关论文
共 46 条
  • [1] Optimized stateful material implication logic for three-dimensional data manipulation
    Adam, Gina C.
    Hoskins, Brian D.
    Prezioso, Mirko
    Strukov, Dmitri B.
    [J]. NANO RESEARCH, 2016, 9 (12) : 3914 - 3923
  • [2] Analysis and comparison on full adder block in submicron technology
    Alioto, M
    Palumbo, G
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) : 806 - 823
  • [3] Statistical Fluctuations in HfOx Resistive-Switching Memory: Part I - Set/Reset Variability
    Ambrogio, Stefano
    Balatti, Simone
    Cubeta, Antonio
    Calderoni, Alessandro
    Ramaswamy, Nirmal
    Ielmini, Daniele
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (08) : 2912 - 2919
  • [4] Analytical Modeling of Oxide-Based Bipolar Resistive Memories and Complementary Resistive Switches
    Ambrogio, Stefano
    Balatti, Simone
    Gilmer, David C.
    Ielmini, Daniele
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (07) : 2378 - 2386
  • [5] [Anonymous], P IEEE ACM INT S NAN
  • [6] [Anonymous], 27 INT S POW TIM MOD
  • [7] [Anonymous], 2012, NANOELECTRONICS INFO
  • [8] [Anonymous], 2015, J LIVER
  • [9] Normally-off Logic Based on Resistive Switches-Part II: Logic Circuits
    Balatti, Simone
    Ambrogio, Stefano
    Ielmini, Daniele
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (06) : 1839 - 1847
  • [10] Normally-off Logic Based on Resistive Switches-Part I: Logic Gates
    Balatti, Simone
    Ambrogio, Stefano
    Ielmini, Daniele
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (06) : 1831 - 1838