The CNNUC3:: An analog I/O 64 x 64 CNN universal machine chip prototype with 7-bit analog accuracy

This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache - on a common silicon substrate. This chip, designed in a 0.5 mum CMOS standard technology contains around 1, 000,000 transistors, 80% of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are in accordance to the CNN Universal Machine [1] paradigm: cellular, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions): random storage/retrieval of intermediate images: capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip Is capable to complete complex spatio-temporal image processing tasks within short computation time ( similar to 200ns for linear convolutions) and using a low power budget (<1.2W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with >7-bit equivalent accuracy in the internal analog operations, which has been confirmed by experimental. measurements. Hence, to all practical purposes, processing tasks completed by the chip have the same accuracy than those completed by digital processors preceded by II-bit digital-to-analog converters for image digitalization. Such 7-bit accuracy is enough for most image processing applications. CNNUC3 has been demonstrated capable to implement - either directly or through template decomposition - 100% of the linear 3 x 3 templates in reported [2].