Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain

被引：5

作者：

Zhao, Xiao ^{[1
,2
]}

Fang, Huajun ^{[3
]}

Ling, Tong ^{[3
]}

Xu, Jun ^{[3
]}

机构：

[1] China Univ Geosci, Key Lab Geodetect, Minist Educ, Beijing, Peoples R China

[2] China Univ Geosci, Sch Geophys & Informat Technol, Beijing 100083, Peoples R China

[3] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2015年 / 69卷 / 03期

基金：

中央高校基本科研业务费专项资金资助;

关键词：

Frequency compensation; Gain enhancement; Two-stage OTA; Low voltage; Process insensitive; CMOS; PERFORMANCE; CIRCUITS;

D O I：

10.1016/j.aeue.2014.12.003

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A proposed low-voltage pseudo-cascode frequency compensation technique to improve the phase-margin of the two-stage OTA in weak-inversion region is introduced. Furthermore, a enhanced composite-transistor technique to increase the DC gain of the two-stage OTA in weak-inversion region is also presented in this paper. Both the proposed techniques achieve enhanced performance without requiring any additional power dissipation. To compare the performance advantages of the proposed techniques, two two-stage OTAs were designed in a UMC 0.18 mu m CMOS process. Simulation results show that the DC gain of the two-stage OTA with enhanced composite-transistor is increased by a factor of 17 dB, the unity-gain bandwidth of the OTA with the proposed pseudo-cascode compensation technique improved 18%, the phase-margin of the OTA is increased by 33%, and it is maintained over a factor of 300 (from 5 to 1500 nA) scaling in its bias current. (C) 2014 Elsevier GmbH. All rights reserved.

引用

页码：685 / 690

页数：6