Formation of Ultra-Shallow Junctions by Advanced Plasma Doping Techniques

The fabrication of advanced CMOS devices calls for production worthy doping solutions to address requirements for increasingly shallow and abrupt junctions, while maintaining high dopant activation to meet series resistance requirements. Plasma Doping (PLAD), which has already been adopted in high volume manufacturing in the ultra high dose, low energy regime for advanced DRAM technology nodes, is now being investigated for source drain extension (SDE) implants, where precise and repeatable dopant placement is critical for maintaining control over device parameters. In this article, we investigate the process performance of SDE implants carried out in a VIISt (R) PLAD system using p- type dopant precursors. Key metrics, such as junction depth, profile abruptness and sheet resistance are reported for as-implanted junctions, as well as samples processed with low thermal budget anneal techniques. Device performance data demonstrating the feasibility of the approach are presented. The advanced control features in the PLAD system are critical in enabling the process performance required for SDE implants.