A generic framework to integrate data caches in the WCET analysis of real-time systems

被引:2
作者
Segarra, Juan [1 ]
Gran Tejero, Ruben [1 ]
Villals, Victor [1 ]
机构
[1] Univ Zaragoza, Dept Informat & Ingn Sistemas, I3A, Zaragoza 50018, Spain
关键词
WCET; Data cache; Data reuse; Real-time; PREDICTION; REUSE;
D O I
10.1016/j.sysarc.2021.102304
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in realtime systems. Caches exploit the inherent reuse properties of programs by temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (set-associative LRU, locked, ACDC, etc.), most of the times adapting techniques designed to analyze instruction caches. On the other hand, there are methodologies to analyze the data reuse of a program, independently of the data cache. In this paper we propose a generic WCET analysis framework to analyze data caches taking profit of such reuse information. It includes the categorization of data references and their integration in an IPET model. We apply it to a conventional LRU cache, an ACDC, and other baseline systems, and compare them using the TACLeBench benchmark suite. Our results show that persistence-based LRU analyses dismiss essential information on data, and a reuse-based analysis improves the WCET bound around 17% in average. In general, the best WCET estimations are obtained with optimization level 2, where the ACDC cache performs 39% better than a set-associative LRU.
引用
收藏
页数:15
相关论文
共 36 条
  • [1] Abel A, 2014, INT SYM PERFORM ANAL, P141, DOI 10.1109/ISPASS.2014.6844475
  • [2] Aho A.V., 2007, ADDISON WESLEY SERIE
  • [3] [Anonymous], P 20 ANN INT S COMP
  • [4] Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems
    Aparicio, Luis C.
    Segarra, Juan
    Rodriguez, Clemente
    Vinals, Victor
    [J]. 16TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS (RTCSA 2010), 2010, : 319 - 328
  • [5] Scope-aware Data Cache Analysis for WCET Estimation
    Bach Khoa Huynh
    Ju, Lei
    Roychoudhury, Abhik
    [J]. 17TH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS 2011), 2011, : 203 - 212
  • [6] Improving the Performance of WCET Analysis in the Presence of Variable Latencies
    Bai, Zhenyu
    Casse, Hugues
    De Michiel, Marianne
    Carle, Thomas
    Rochange, Christine
    [J]. 21ST ACM SIGPLAN/SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS (LCTES '20), 2020, : 119 - 130
  • [7] Improving the first-miss computation in set-associative instruction caches
    Ballabriga, Clement
    Casse, Hugues
    [J]. ECRTS 2008: PROCEEDINGS OF THE 20TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS, 2008, : 341 - 350
  • [8] Bonenfant A., 2008, P WORKSH RES AN
  • [9] Exact analysis of the cache behavior of nested loops
    Chatterjee, S
    Parker, E
    Hanlon, PJ
    Lebeck, AR
    [J]. ACM SIGPLAN NOTICES, 2001, 36 (05) : 286 - 297
  • [10] Unified Cache Modeling for WCET Analysis and Layout Optimizations
    Chattopadhyay, Sudipta
    Roychoudhury, Abhik
    [J]. 2009 30TH IEEE REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2009, : 47 - 56