A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance

被引:0
作者
Xu, Ke [1 ,2 ]
Li, Yu [1 ]
Huang, Bo [1 ]
Liu, Xiangkai [1 ]
Wang, Hong [1 ]
Wu, Zhuoyan [1 ]
Yan, Zhanpeng [1 ]
Tu, Xueying [1 ]
Wu, Tongqing [1 ]
Zeng, Daibing [1 ]
机构
[1] ZTE Microelect Res Inst, Beijing, Peoples R China
[2] State Key Lab Mobile Network & Mobile Multimedia, Shenzhen, Guangdong, Peoples R China
来源
PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED '18) | 2018年
关键词
Bandwidth compression; DVFS; encoder; HEVC; low-power;
D O I
10.1145/3218603.3218604
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the design and VLSI implementation of a low-power HEVC main profile encoder, which is able to process up to 4096x2160@30fps 4:2:0 encoding in real-time with five-stage pipeline architecture. A pyramid ME (Motion Estimation) engine is employed to reduce search complexity. To compensate for the video sequences with fast moving objects, GME (Global Motion Estimation) are introduced to alleviate the effect of limited search range. We also implement an alternative 5x5 search along with 3x3 to boost video quality. For intra mode decision, original pixels, instead of reconstructed ones are used to reduce pipeline stall. The encoder supports DVFS (Dynamic Voltage and Frequency Scaling) and features three operating modes, which helps to reduce power consumption by 25%. Scalable quality that trades encoding quality for power by reducing size of search range and intra prediction candidates, achieves 11.4% power reduction with 3.5% quality degradation. Furthermore, a lossless frame buffer compression is proposed which reduced DDR bandwidth by 49.1% and power consumption by 13.6%. The entire video surveillance SoC is fabricated with TSMC 28nm technology with 1.96 mm(2) area. It consumes 2.88M logic gates and 117KB SRAM. The measured power consumption is 103mW at 350MHz for 4K encoding with high-quality mode. The 0.39nJ/pixel of energy efficiency of this work, which achieves 42% similar to 97% power reduction as compared with reference designs, make it ideal for real-time low-power smart video surveillance applications.
引用
收藏
页码:213 / 218
页数:6
相关论文
共 8 条
  • [1] HEVC Complexity and Implementation Analysis
    Bossen, Frank
    Bross, Benjamin
    Suehring, Karsten
    Flynn, David
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2012, 22 (12) : 1685 - 1696
  • [2] Guo J, 2016, INT WORKS POW TIM, P84, DOI 10.1109/PATMOS.2016.7833430
  • [3] Survey on block matching motion estimation algorithms and architectures with new results
    Huang, YW
    Chen, CY
    Tsai, CH
    Shen, CF
    Chen, LG
    [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 42 (03): : 297 - 320
  • [4] Oh K., 2016, INT C SYST SIGN IM P, P483
  • [5] Onishi T, 2015, SYMP VLSI CIRCUITS
  • [6] Overview of the High Efficiency Video Coding (HEVC) Standard
    Sullivan, Gary J.
    Ohm, Jens-Rainer
    Han, Woo-Jin
    Wiegand, Thomas
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2012, 22 (12) : 1649 - 1668
  • [7] Tsai S-F, 2013, 2013 S VLSIC, P188
  • [8] Xu K, 2007, ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P256, DOI 10.1145/1283780.1283835