Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing

被引:10
作者
He, Wangxin [1 ]
Shim, Wonbo [2 ]
Yin, Shihui [1 ]
Sun, Xiaoyu [2 ]
Fan, Deliang [1 ]
Yu, Shimeng [2 ]
Seo, Jae-sun [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA
[2] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
来源
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2021年
关键词
RRAM; in-memory computing; multi-level cell; relaxation effect; deep neural network; NEURAL-NETWORKS; CHIP;
D O I
10.1109/IRPS46558.2021.9405228
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this paper, we investigate the relaxation effects on multi-level resistive random access memory (RRAM) based in-memory computing (IMC) for deep neural network (DNN) inference. We characterized 2-bit-per-cell RRAM IMC prototypes and measured the relaxation effects over 100 hours on multiple 8 kb test chips, where the relaxation is found to be most severe in the two intermediate states. We incorporated the experimental data into SPICE simulation and software DNN inference, showing DNN accuracy for CIFAR-10 dataset could degrade from 87.35% to 11.58% after 144 hours. To recover the largely degraded accuracy, mitigation schemes are proposed: 1) at the circuit level, the reference voltage for RRAM IMC could be calibrated after 80 hours when the relaxation is saturated. 2) At the algorithm level, the weights are trained with lower percentages to be quantized to the two intermediate states. With both schemes applied, the accuracy could be recovered to 87.32% for long-term stability.
引用
收藏
页数:7
相关论文
共 12 条
[1]  
Degraeve R., 2016, P IRPS
[2]   Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey [J].
Deng, Lei ;
Li, Guoqi ;
Han, Song ;
Shi, Luping ;
Xie, Yuan .
PROCEEDINGS OF THE IEEE, 2020, 108 (04) :485-532
[3]   2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning [J].
He, Wangxin ;
Yin, Shihui ;
Kim, Yulhwa ;
Sun, Xiaoyu ;
Kim, Jae-Joon ;
Yu, Shimeng ;
Seo, Jae-Sun .
IEEE SOLID-STATE CIRCUITS LETTERS, 2020, 3 :194-197
[4]  
Ho CH, 2017, INT EL DEVICES MEET
[5]  
Hsieh E. R., 2019, IEEE INT ELECT DEVIC, DOI 10.1109/IEDM19573.2019.8993514.
[6]  
Liu Q, 2020, ISSCC DIG TECH PAP I, P500, DOI 10.1109/ISSCC19947.2020.9062953
[7]   Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine [J].
Shim, Wonbo ;
Luo, Yandong ;
Seo, Jae-Sun ;
Yu, Shimeng .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (06) :2318-2323
[8]  
Wan WE, 2020, ISSCC DIG TECH PAP I, P498, DOI 10.1109/ISSCC19947.2020.9062979
[9]   Relaxation Effect in RRAM Arrays: Demonstration and Characteristicsn [J].
Wang, Chen ;
Wu, Huaqiang ;
Gao, Bin ;
Dai, Lingjun ;
Deng, Ning ;
Sekar, D. C. ;
Lu, Z. ;
Kellam, M. ;
Bronner, G. ;
Qian, He .
IEEE ELECTRON DEVICE LETTERS, 2016, 37 (02) :182-185
[10]   15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices [J].
Xue, Cheng-Xin ;
Huang, Tsung-Yuan ;
Liu, Je-Syu ;
Chang, Ting-Wei ;
Kao, Hui-Yao ;
Wang, Jing-Hong ;
Liu, Ta-Wei ;
Wei, Shih-Ying ;
Huang, Sheng-Po ;
Wei, Wei-Chen ;
Chen, Yi-Ren ;
Hsu, Tzu-Hsiang ;
Chen, Yen-Kai ;
Lo, Yun-Chen ;
Wen, Tai-Hsing ;
Lo, Chung-Chuan ;
Liu, Ren-Shun ;
Hsieh, Chih-Cheng ;
Tang, Kea-Tiong ;
Chang, Meng-Fan .
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, :244-+