Multibuffer delay line architectures for efficient contention resolution in optical switching nodes

被引:67
作者
Chlamtac, I
Fumagalli, A
Suh, CJ
机构
[1] Boston Univ, Dept Elect Comp & Syst Engn, Boston, MA 02215 USA
[2] Samsung Elect Co, Network Res Lab, Seoul, South Korea
基金
美国国家科学基金会;
关键词
contention resolution; multibuffer delay line; optical delay line; optical packet switching;
D O I
10.1109/26.891219
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes an efficient contention resolution snitching architecture which can serve as the basis for all-optical switching nodes. The presented solution builds on fiber delay lines used as temporary optical storage and 2 x 2 space photonic switches, a solution principle also known as Quadro or switched delay lines (SDLs). The efficiency of SDLs is fundamentally linked to its storage capacity, i.e., the length of the fiber delay lines, while its cost depends on the number of 2 x 2 photonic switches, i.e., the number of stages in the switch. This work presents a solution that makes use of multibuffer fiber delay lines which allow multiple packets to be concurrently stored (propagated) on each line. With a novel switch control, it is shown that this solution increases the total storage capacity and significantly improves switch and network performance, without increasing the number of the 2 x 2 switches in the system, i.e., its cost.
引用
收藏
页码:2089 / 2098
页数:10
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