Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis

被引：52

作者：

Chen, Yibo ^{[1
]}

Niu, Dimin ^{[1
]}

Xie, Yuan ^{[1
]}

Chakrabarty, Krishnendu ^{[2
]}

机构：

[1] Penn State Univ, Dept Comp Sci & Engn, University Pk, PA 16803 USA

[2] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA

来源：

2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2010年

基金：

美国国家科学基金会;

关键词：

YIELD;

D O I：

10.1109/ICCAD.2010.5653753

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging technology as a mainstream design approach, designers must consider the cost of 3D integration. IC testing is a key factor that affects the final product cost, and it could be a major portion of the total IC cost. In 3D IC design, various testing strategies and different integration methods could affect the final product cost dramatically, and the interaction with other cost factors could result in various trade-offs. This paper develops a comprehensive and parameterized testing cost model for 3D IC integration, and analyzes the trade-offs associated with testing strategies and testing circuit overheads. With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips.

引用

页码：471 / 476

页数：6

共 20 条

[1]

[Anonymous], 2009, PROC IEEE INT C 3D S

[2]

Chan MS, 2009, INT SYM QUAL ELECT, P241, DOI 10.1109/ISQED.2009.4810301

[3] On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification [J].

Chen, Po-Yuan ;

Wu, Cheng-Wen ;

Kwai, Ding-Ming .

2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2009, :450-+

[4] Demystifying 3D ICs: The procs and cons of going vertical [J].

Davis, WR ;

Wilson, J ;

Mick, S ;

Xu, M ;

Hua, H ;

Mineo, C ;

Sule, AM ;

Steer, M ;

Franzon, PD .

IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (06) :498-510

[5]

Dong XY, 2009, ASIA S PACIF DES AUT, P234, DOI 10.1109/ASPDAC.2009.4796486

[6] Strategies for improving the parametric yield and profits of 3D ICs [J].

Ferri, Cesare ;

Reda, Sherief ;

Bahar, R. Iris .

IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, :220-226

[7] Test Challenges for 3D Integrated Circuits [J].

Lee, Hsien-Hsin S. ;

Chakrabarty, Krishnendu .

IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (05) :26-35

[8] Testing Circuit Partitioned 3D IC Designs [J].

Lewis, Dean L. ;

Lee, Hsien Hsin S. .

2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2009, :139-144

[9]

Marinissen Erik Jan, 2009, Proceedings of the 2009 IEEE International Test Conference (ITC 2009), DOI 10.1109/TEST.2009.5355674

[10] Yield and cost modeling for 3D chip stack technologies [J].

Mercier, P. ;

Singh, S. R. ;

Iniewski, K. ;

Moore, B. ;

O'Shea, P. .

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, :357-360

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