Global interconnect optimization in the presence of on-chip inductance

As technology advances, global interconnects in upper metal layers exhibit significant inductive effect with faster signal rise and fall times. Therefore, existing optimization schemes which optimize various performance parameters of global interconnects, such as, latency, bandwidth, repeater area, and power consumption based on RC delay models will be affected by on-chip inductance and will lead to degraded chip performance. This paper will examine the impacts of inductance on these performance parameters, which were previously based on RC models. This paper will also attempt to identify the limitations of these figures of merit (FOMs), and address the impact of line inductance on the methodology of global interconnect width and spacing optimization, and on different figures of merit.