A 25μm pitch LWIR staring focal plane array with pixel-level 15-bit ADC ROIC achieving 2mK NETD

CEA-Leti MINATEC has been involved in infrared focal plane array (IRFPA) development since many years, with performing HgCdTe in-house process from SWIR to LWIR and more recently in focusing its work on new ROIC architectures. The trend is to integrate advanced functions into the CMOS design for the purpose of applications demanding a breakthrough in Noise Equivalent Temperature Difference (NETD) performances (reaching the mK in LWIR band) or a high dynamic range (HDR) with high-gain APDs. In this paper, we present a mid-TV format focal plane array (FPA) operating in LWIR with 25 mu m pixel pitch, including a new readout IC (ROIC) architecture based on pixel-level charge packets counting. The ROIC has been designed in a standard 0.18 mu m 6-metal CMOS process, LWIR n/p HgCdTe detectors were fabricated with CEA-Leti in-house process. The FPA operates at 50Hz frame rate in a snapshot integrate-while-read (IWR) mode, allowing a large integration time. While classical pixel architectures are limited by the charge well capacity, this architecture exhibits a large well capacity (near 3Ge-) and the 15-bit pixel level ADC preserves an excellent signal-to-noise ratio (SNR) at full well. These characteristics are essential for LWIR FPAs as broad intra-scene dynamic range imaging requires high sensitivity. The main design challenges for this digital pixel array (SNR, power consumption and layout density) are discussed. The electro-optical results demonstrating a peak NETD value of 2mK and images taken with the FPA are presented. They validate both the pixel-level ADC concept and its circuit implementation. A previously unreleased SNR of 90dB is achieved.